University of Delaware Department of Electrical and Computer Engineering Computer Architecture and Parallel Systems Laboratory Experiments with the Fresh Breeze Tree-Based Memory Model

Recent developments have brought to the forefront some pressing and difficult problems concerning the usability of computer systems: lack of a satisfactory general purpose programming model for parallel computation; how to achieve efficient utilization of processing and memory resources; and system resilience in the presence of malicious attacks and the expectation that future hardware will be more susceptible to faults. These problems have been exacerbated in the shift to multi-core and many-core processing chips and the evident future dominance of massively parallel computing platforms. The Fresh Breeze memory model and system architecture is proposed as an approach to achieving significant improvements in all three problem areas. In contrast with conventional computer systems and their storage hierarchies, a Fresh Breeze system is envisioned to support fine-grain management of memory and processing resources and to utilize a global shared name space for all processors and computation tasks. Scheduling of tasks and storage allocation are done by hardware realizations, eliminating nearly all operating system execution cycles for data access, task scheduling and security. In particular, the Fresh Breeze memory model uses trees of fixed-size chunks of memory to represent all data objects. The experiments described in this paper use simulation of a Fresh Breeze system with a two-level memory hierarchy using 128-byte chunks and up to 40 processor cores. Simulation experiments are run using the FAST simulator for the Cyclops 64 many-core chip. A test program, the vector dot product, was written in the Cyclops C language using new libraries of routines for task scheduling and simulation of the novel memory model. Results to date demonstrate that: (1) Fine-grain hardware-implemented resource management mechanisms can support massive parallelism and high processor utilization through the latency-hiding properties of multi-tasking; and (2) hardware implementation of a work stealing scheme incorporated in our simulation can effectively distribute tasks over the processors of a manycore parallel computer.